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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max1202/max1203 are 12-bit data-acquisition systems specifically designed for use in applications with mixed +5v (analog) and +3v (digital) supply volt- ages. they operate with a single +5v analog supply or dual ?v analog supplies, and combine an 8-channel multiplexer, high-bandwidth track/hold, and serial inter- face with high conversion speed and low power con- sumption. a 4-wire serial interface connects directly to spi/microwire devices without external logic, and a serial strobe output allows direct connection to tms320-family digital signal processors. the max1202/max1203 use either the internal clock or an external serial-interface clock to perform successive- approximation analog-to-digital conversions. the serial interface operates at up to 2mhz. the max1202 features an internal 4.096v reference, while the max1203 requires an external reference. both parts have a reference-buffer amplifier that simplifies gain trim. they also have a vl pin that is the power supply for the digital outputs. output logic levels (3v, 3.3v, or 5v) are determined by the value of the voltage applied to this pin. these devices provide a hard-wired shdn pin and two software-selectable power-down modes. accessing the serial interface automatically powers up the devices. a quick turn-on time enables the max1202/max1203 to be shut down between conversions, allowing the user to optimize supply currents. by customizing power- down between conversions, supply current can drop below 10? at reduced sampling rates. the max1202/max1203 are available in 20-pin ssop and dip packages, and are specified for the commer- cial, extended, and military temperature ranges. applications 5v/3v mixed-supply systems data acquisition high-accuracy process control battery-powered instruments medical instruments features ? 8-channel single-ended or 4-channel differential inputs ? operates from single +5v or dual ?v supplies ? user-adjustable output logic levels (2.7v to 5.25v) ? low power: 1.5ma (operating mode) 2? (power-down mode) ? internal track/hold, 133khz sampling rate ? internal 4.096v reference (max1202) ? spi/microwire/tms320-compatible 4-wire serial interface ? software-configurable unipolar/bipolar inputs ? 20-pin dip/ssop max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 top view dip/ssop v dd sclk cs din sstrb dout vl gnd refadj ref shdn v ss ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max1202 max1203 pin configuration 19-1173; rev 2; 5/98 evaluation kit available typical operating circuit appears at end of data sheet. spi is a registered trademark of motorola, inc. microwire is a registered trademark of national semiconductor corp. ordering information continued at end of data sheet. * dice are specified at t a = +25?, dc parameters only. ? dice* 0? to +70? max1202bc/d max1202bcap max1202acap max1202bcpp max1202 acpp part temp. range 0? to +70? 0? to +70? 0? to +70? 0? to +70? 20 ssop 20 ssop 20 plastic dip 20 plastic dip pin-package inl (lsb) ?/2 ? ?/2 ? ordering information
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ................................................................-0.3v to 6v vl ...............................................................-0.3v to (v dd + 0.3v) v ss to gnd .................................................................0.3v to -6v v dd to v ss ................................................................-0.3v to 12v ch0?h7 to gnd ............................(v ss - 0.3v) to (v dd + 0.3v) ch0?h7 total input current...........................................?0ma ref to gnd ................................................-0.3v to (v dd + 0.3v) refadj to gnd .........................................-0.3v to (v dd + 0.3v) digital inputs to gnd .................................-0.3v to (v dd + 0.3v) digital outputs to gnd .................................-0.3v to (vl + 0.3v) digital output sink current .................................................25ma continuous power dissipation (t a = +70?) plastic dip (derate 11.11mw/? above +70?) ...........889mw ssop (derate 8.00mw/? above +70?) .....................640mw cerdip (derate 11.11mw? above +70?) .................889mw operating temperature ranges max1202_c_p/max1203_c_p ............................0? to +70? max1202_e_p/max1203_e_p..........................-40? to +85? max1202bmjp/max1203bmjp .....................-55? to +125? storage temperature range .............................-60? to +150? lead temperature (soldering, 10sec) .............................+300? electrical characteristics (v dd = +5v ?%, vl = 2.7v to 3.6v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1202?.7? capacitor at ref pin; max1203?xternal reference, v ref = 4.096v applied to ref pin; t a = t min to t max ; unless otherwise noted.) -3db rolloff mhz 4.5 max1202a/max1203a small-signal bandwidth khz 800 v in = 4.096vp-p, 65khz (note 4) external reference, 4.096v max1202b/max1203b no missing codes over temperature conditions full-power bandwidth ? max1202 (all grades) db -85 channel-to-channel crosstalk db 80 sfdr spurious-free dynamic range db -80 thd total harmonic distortion (up to the 5th harmonic) db 70 sinad signal-to-noise + distortion ratio lsb ?.5 inl relative accuracy (note 2) bits 12 resolution lsb ?.1 channel-to-channel offset matching ppm/? ?.8 gain temperature coefficient ?.0 lsb ?.0 dnl differential nonlinearity units min typ max symbol parameter lsb ?.0 offset error ?.5 lsb ? gain error (note 3) external reference, 4.096v max1203a max1203b dc accuracy (note 1) dynamic specifications (10khz sine-wave input, 4.096vp-p, 133ksps, 2.0mhz external clock, bipolar-input mode)
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5v ?%, vl = 2.7v to 3.6v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1202?.7? capacitor at ref pin; max1203?xternal reference, v ref = 4.096v applied to ref pin; t a = t min to t max ; unless otherwise noted.) max1202ac t a = +25? external clock, 2mhz, 12 clocks/conversion (note 6) on/off leakage current, v ch_ = ?v bipolar, v ss = -5v unipolar, v ss = 0v 6 used for data transfer only internal compensation mode (note 6) internal clock max1202ae external compensation mode external compensation mode, 4.7? ?0 60 conditions ppm/? ?0 50 v ref temperature coefficient ma 30 ref short-circuit current v 4.076 4.096 4.116 ref output voltage pf 16 input capacitance ? ?.01 ? multiplexer leakage current ? ref /2 4.7 v v ref input voltage range, single- ended and differential (note 7) 0 2.0 ?0 0.1 0.4 max1202b ? mhz 0.1 2.0 external clock frequency range mhz 1.7 internal clock frequency 0.01 0ma to 0.5ma output load mv 2.5 load regulation (note 8) ns 10 aperture delay ? 1.5 t acq track/hold acquisition time ? 5.5 10 t conv conversion time (note 5) internal compensation mode ? 0 capacitive bypass at ref capacitive bypass at refadj units min typ max symbol parameter ps % ?.5 refadj adjustment range v 2.50 v dd + 50mv input voltage range ? 200 350 input current k w 12 20 input resistance shdn = 0v ? 1.5 10 ref input current in shutdown v v dd - 50mv refadj buffer disable threshold <50 aperture jitter conversion rate internal reference (max1202 only, reference-buffer enabled) analog input external reference at ref (reference buffer disabled, v ref = 4.096v)
? max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +5v ?%, vl = 2.7v to 3.6v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1202?.7? capacitor at ref pin; max1203?xternal reference, v ref = 4.096v applied to ref pin; t a = t min to t max ; unless otherwise noted.) operating mode ma 1.5 2.5 internal compensation mode v dd = 5v ?%; external reference, 4.096v; full-scale input mv ?.06 ?.5 v fast power-down (note 9) 30 70 external compensation mode max1202 max1202 conditions 2.70 5.25 vl logic supply voltage vl = v dd = 5v ? 10 i vl logic supply current (notes 6, 10) psr positive supply rejection (note 11) v ss = -5v ?%; external reference, 4.096v; full-scale input mv ?.01 ?.5 psr negative supply rejection (note 11) external reference, 4.096v; full-scale input mv ?.06 ?.5 psr logic supply rejection (note 12) ? ? 0 capacitive bypass at ref v 0 or -5 ?% v ss negative supply voltage v 5 ?% v dd positive supply voltage 4.7 1.68 ?0 units min typ max symbol parameter max1203 v/v 1.64 reference-buffer gain max1203 ? ? refadj input current full power-down 10 operating mode and fast power-down ? 50 i ss negative supply current full power-down (note 9) ? i dd 210 positive supply current external reference at refadj power requirements
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = +5v ?%, vl = 2.7v to 3.6v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1202?.7? capacitor at ref pin; max1203?xternal reference, v ref = 4.096v applied to ref pin; t a = t min to t max ; unless otherwise noted.) cs = vl (note 6) cs = vl i source = 1ma i sink = 3ma shdn = open shdn = 0v shdn = v dd (note 6) v in = 0v or v dd shdn = open i sink = 5ma conditions pf 15 c out three-state output capacitance ? ?0 i l three-state leakage current v vl - 0.5 v oh output voltage high v 0.4 v ol output voltage low na -100 100 shdn maximum allowed leakage, mid-input v 2.75 v flt shdn voltage, floating ? -4.0 i sl shdn input current, low ? 4.0 i sh shdn input current, high v v dd - 0.5 v sh shdn input high voltage v 0.4 v ol output voltage low v 0.8 v il v 2.0 v ih din, sclk, cs input high voltage din, sclk, cs input low voltage i sink = 8ma 0.3 v 1.5 v dd - 1.5 i sink = 6ma v sm 0.3 pf 15 c in din, sclk, cs input capacitance ? ? i in din, sclk, cs input leakage shdn input mid-voltage i source = 1ma v v 0.15 v hyst din, sclk, cs input hysteresis 4 v oh output voltage high cs = 5v ? ?0 i l three-state leakage current units min typ max symbol parameter cs = 5v (note 6) pf 15 c out three-state output capacitance v 0.5 v sl shdn input low voltage digital inputs: din, sclk, c c s s , s s h h d d n n digital outputs: dout, sstrb (vl = 2.7v to 3.6v) digital outputs: dout, sstrb (vl = 4.75v to 5.25v)
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 6 _______________________________________________________________________________________ timing characteristics (v dd = +5v ?%, vl = 2.7v to 3.6v, v ss = 0v or -5v ?%, t a = t min to t max , unless otherwise noted.) note 1: tested at v dd = 5.0v; v ss = 0v; unipolar-input mode. note 2: relative accuracy is the analog value? deviation (at any code) from its theoretical value after the full-scale range is calibr ated. note 3: max1202?nternal reference, offset nulled; max1203?xternal reference (v ref = 4.096v), offset nulled. note 4: on-channel grounded; sine wave applied to all off-channels. note 5: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: guaranteed by design. not subject to production testing. note 7: common-mode range for analog inputs is from v ss to v dd . note 8: external load should not change during the conversion for specified accuracy. note 9: shutdown supply current is measured with vl at 3.3v, and with all digital inputs tied to either vl or gnd; refadj = gnd. shutdown supply current is also dependent on v ih (figure 12c). note 10: logic supply current is measured with the digital outputs (dout and sstrb) disabled ( cs high). when the outputs are active ( cs low), the logic supply current depends on f sclk , and on the static and capacitive load at dout and sstrb. note 11: measured at v supply + 5% and v supply - 5% only. note 12: measured at vl = 2.7v and vl = 3.6v. ns 100 t css external-clock mode only, c load = 100pf ns cs to sclk rise setup 240 c load = 100pf ns ns 20 240 ns 0 t do sclk fall to output data valid t csh conditions cs to sclk rise hold 240 t dv cs fall to output enable c load = 100pf ns 240 t tr cs rise to output disable t sdv cs fall to sstrb output enable (note 6) external-clock mode only, c load = 100pf ns 240 t str cs rise to sstrb output disable (note 6) internal-clock mode only ns 0 t sck sstrb rise to sclk rise (note 6) ns 200 t ch sclk pulse width high ns 200 t cl sclk pulse width low c load = 100pf ns 240 t sstrb sclk fall to sstrb c load = 100pf ns 0 t dh din to sclk hold ? 1.5 t acq acquisition time ns 100 t ds din to sclk setup units min typ max symbol parameter
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface _______________________________________________________________________________________ 7 1.0 2.0 1.8 1.6 1.4 1.2 4.5 supply current vs. supply voltage max1202 toc01 supply voltage (v) supply current (ma) 5.3 4.7 5.1 5.5 4.9 max1202 max1203 0 -60 supply current vs. temperature 0.5 max1202 toc02 temperature (?) supply current (ma) 100 2.0 1.0 1.5 -20 60 140 3.0 2.5 20 max1202 max1203 6 5 0 -60 shutdown supply current vs. temperature 4 max1202 toc03 temperature ( c) shutdown supply current ( m a) 60 2 1 -20 20 3 100 140 refadj = gnd full power-down 0.8 0.6 0.7 0.5 0 -60 integral nonlinearity vs. temperature 0.4 max1202 toc04 temperature ( c) inl (lsb) 60 0.2 0.1 -20 20 0.3 100 140 3 2 -3 -60 channel-to-channel offset-error matching vs. temperature 1 max1202 toc07 temperature ( c) offset-error matching (lsb) 60 -1 -2 -20 20 0 100 140 2.0 1.0 1.5 0.5 -2.0 -60 offset error vs. temperature 0 max1202 toc05 temperature ( c) offset error (lsb) 60 -1.0 -1.5 -20 20 -0.5 100 140 5 3 4 1 2 0 -5 -60 gain error vs. temperature -1 max1202 toc06 temperature ( c) gain error (lsb) 60 -3 -4 -20 20 -2 100 140 differential single-ended 5 3 4 1 2 0 -5 -60 channel-to-channel gain-error matching vs. temperature -1 max1202 toc08 temperature ( c) gain-error matching (lsb) 60 -3 -4 -20 20 -2 100 140 __________________________________________typical operating characteristics (v dd = 5v ?%; vl = 2.7v to 3.6v; v ss = 0v; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1202?.7? capacitor at ref pin; max1203?xternal reference, v ref = 4.096v applied to ref pin; t a = +25?; unless otherwise noted.)
______________________________________________________________pin description max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 8 _______________________________________________________________________________________ -1.0 -0.8 -0.6 -0.4 0 integral nonlinearity vs. digital 1.0 0.4 0.6 0.8 max1202 toc09 digital code inl (lsb) 3000 0 -0.2 750 1500 2250 0.2 3750 4500 -120 0 fft plot 20 max1202 toc10 frequency (khz) amplitude (db) -20 -40 -60 -80 -100 33.25 0 66.50 v ss = -5v ____________________________typical operating characteristics (continued) (v dd = 5v ?%; vl = 2.7v to 3.6v; v ss = 0v; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1202?.7? capacitor at ref pin; max1203?xternal reference, v ref = 4.096v applied to ref pin; t a = +25?; unless otherwise noted.) serial-strobe output. in internal clock mode, sstrb goes low when the max1202/max1203 begin the analog-to-digital conversion, and goes high when the conversion is finished. in external clock mode, sstrb pulses high for one clock period before the msb decision. high impedance when cs is high (external clock mode). sstrb 16 serial-data input. data is clocked in at sclk? rising edge. din 17 active-low chip select. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. cs 18 serial-clock input. sclk clocks data in and out of the serial interface. in external clock mode, sclk also sets the conversion speed. (duty cycle must be 40% to 60% in external clock mode.) sclk 19 positive supply voltage, +5v ?% v dd 20 input to the reference-buffer amplifier. tie refadj to v dd to disable the reference-buffer amplifier. refadj 12 ground; in- input for single-ended conversions gnd 13 supply voltage for digital output pins. voltage applied to vl determines the positive output swing of the digital outputs (dout, sstrb). 2.7v vl 5.25v. vl 14 serial-data output. data is clocked out at sclk? falling edge. high impedance when cs is high. dout 15 reference-buffer output/adc reference input. in internal reference mode (max1202 only), the refer- ence buffer provides a 4.096v nominal output, externally adjustable at refadj. in external reference mode, disable the internal buffer by pulling refadj to v dd. ref 11 three-level shutdown input. pulling shdn low shuts the max1202/max1203 down to 10? (max) supply current; otherwise, the max1202/max1203 are fully operational. pulling shdn to v dd puts the reference-buffer amplifier in internal compensation mode. letting shdn float puts the reference- buffer amplifier in external compensation mode. shdn 10 pin negative supply voltage. tie v ss to -5v ?% or to gnd. v ss 9 sampling analog inputs ch0?h7 1? function name
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface _______________________________________________________________________________________ 9 _______________detailed description the max1202/max1203 analog-to-digital converters (adcs) use a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog signal to a 12-bit digital output. a flexible ser- ial interface provides easy interface to 3v microproces- sors (?s). figure 3 is the max1202/max1203 block diagram. pseudo-differential input figure 4 shows the adc? analog comparator? sam- pling architecture. in single-ended mode, in+ is inter- nally switched to ch0?h7 and in- is switched to gnd. in differential mode, in+ and in- are selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. configure the channels using tables 3 and 4. in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo-differential such that only the signal at in+ is sampled. the return side (in-) must remain stable (typi- cally within ?.5lsb, within ?.1lsb for best results) with respect to gnd during a conversion. to do this, connect a 0.1? capacitor from in- (of the selected analog input) to gnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and ends on the falling sclk edge after the input control word? last bit is entered. the t/h switch opens at the end of the acquisition interval, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex- er switching c hold from the positive input (in+) to the negative input (in-). in single-ended mode, in- is sim- ply gnd. this unbalances node zero at the compara- tor? input. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equivalent to transferring a charge of 16pf x [(v in +) - (v in -)] from c hold to the binary- weighted capacitive dac, which in turn forms a digital representation of the analog input signal. figure 1. load circuits for enable time figure 2. load circuits for disable time figure 3. block diagram +3.3v 3k c load gnd dout c load gnd 3k dout a. high-z to v oh and v ol to v oh b. high-z to v ol and v oh to v ol +3.3v 3k c load gnd dout c load gnd 3k dout a. v oh to high-z b. v ol to high-z input shift register control logic int clock output shift register +2.44v reference t/h analog input mux 12-bit sar adc in dout sstrb v dd vl v ss sclk din ch0 ch1 ch3 ch2 ch7 ch6 ch5 ch4 gnd refadj ref out ref clock +4.096v 20k ? 1.68 1 2 3 4 5 6 7 8 10 11 12 13 15 16 17 18 19 max1202 max1203 (max1202) cs shdn a 20 14 9
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 10 ______________________________________________________________________________________ track/hold the t/h enters tracking mode on the falling clock edge after the fifth bit of the 8-bit control word is shifted in. the t/h enters hold mode on the falling clock edge after the eighth bit of the control word is shifted in. in- is con- nected to gnd if the converter is set up for single-ended inputs, and the converter samples the ??input. in- con- nects to the ??input if the converter is set up for differen- tial inputs, and the difference of ? |n+ - in- ? is sampled. the positive input connects back to in+, at the end of the conversion, and c hold charges to the input signal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, acquisition time increases and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. it is calculated by the following: t acq = 9 x (r s + r in ) x 16pf where r in = 9k , r s = the source impedance of the input signal, and t acq is never less than 1.5?. source impedances below 1k w do not significantly affect the adc? ac performance. higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in figure 5. note that the input capaci- tor forms an rc filter with the input source impedance, limiting the adc? signal bandwidth. figure 5. quick-look circuit ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 gnd c switch track t/h switch 9k r in c hold hold 12-bit capacitive dac ref zero comparator + 16pf single-ended mode: in+ = cho?h7, in- = gnd. differential mode: at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, ch6/ch7. 0.1? 4.7? v dd gnd v ss cs sclk din dout sstrb shdn +3v n.c. 0.01? ch7 vl refadj +2.5v reference ref c2 0.01? c1 4.7? +2.5v ** 0v to 4.096v analog input 0.1? +3v oscilloscope ch1 ch2 ch3 ch4 *full-scale analog input, conversion result = $fff (hex). **required for max1203 only. max1202 max1203 +5v 2mhz oscillator sclk sstrb dout* figure 4. equivalent input circuit
table 1a. unipolar full scale and zero scale max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ______________________________________________________________________________________ 11 input bandwidth the adc? input tracking circuitry has a 4.5mhz small-signal bandwidth. therefore it is possible to digi- tize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input range and input protection internal protection diodes, which clamp the analog inputs to v dd and v ss , allow the analog input pins to swing from (v ss - 0.3v) to (v dd + 0.3v) without dam- age. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv, or be lower than v ss by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not forward bias the protection diodes of off-channels more than 2ma. the full-scale input voltage depends on the voltage at ref (tables 1a and 1b). quick look use the circuit of figure 5 to quickly evaluate the max1202/max1203? analog performance. the max1202/max1203 require a control byte to be written to din before each conversion. tying din to +3v feeds in control byte $ff hex, which triggers single-ended unipolar conversions on ch7 in external clock mode without powering down between conversions. in exter- nal clock mode, the sstrb output pulses high for one clock period before the most significant bit of the 12-bit conversion result shifts out of dout. varying the ana- log input to ch7 alters the sequence of bits from dout. a total of 15 clock cycles per conversion is required. all sstrb and dout output transitions occur on sclk? falling edge. how to start a conversion clocking a control byte into din starts conversion on the max1202/max1203. with cs low, each rising edge on sclk clocks a bit from din into the max1202/ max1203? internal shift register. after cs falls, the first logic ??bit defines the control byte? msb. until this first ?tart?bit arrives, any number of logic ??bits can be clocked into din with no effect. table 2 shows the control-byte format. the max1202/max1203 are fully compatible with spi/microwire devices. for spi, select the correct clock polarity and sampling edge in the spi control reg- isters: set cpol = 0 and cpha = 0. microwire and spi both transmit and receive a byte at the same time. using the typical operating circuit , the simplest soft- ware interface requires only three 8-bit transfers to per- form a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the 12-bit conversion result). table 1b. bipolar full scale, zero scale, and negative full scale reference external zero scale 0v 0v at refadj at ref full scale v refadj x a* v ref 0v internal +4.096v -1/2 v refadj x a* -1/2 v ref negative full scale -4.096v / 2 +1/2 v ref +1/2 v refadj x a* 0v 0v +4.096v / 2 full scale 0v zero scale at refadj external reference internal at ref * a = 1.68 for the max1202, 1.64 for the max1203. * a = 1.68 for the max1202, 1.64 for the max1203.
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 12 ______________________________________________________________________________________ table 2. control-byte format table 3. channel selection in single-ended mode (sgl/ d d i i f f = 1) sel1 sel0 0 0 0 ch4 ch5 sel2 ch6 ch7 gnd 1 0 0 + 0 0 1 + 1 0 ch0 + 1 + 0 1 ch1 0 + 1 1 ch3 0 + 0 1 ch2 1 + 1 1 1 + table 4. channel selection in differential mode (sgl/ d d i i f f = 0) sel1 sel0 0 0 0 ch4 ch5 sel2 ch6 ch7 0 0 1 + 0 1 0 + 0 1 ch0 + 1 + 1 0 ch1 0 + 1 0 ch3 1 + 1 1 ch2 0 + 1 1 1 + pd0 bit 0 (lsb) sgl/ dif bit 2 pd1 bit 1 uni/ bip bit 3 sel 0 bit 4 bit 7 (msb) sel 1 sel 2 start bit 5 bit 6 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0v to v ref can be converted; in bipolar mode, the signal can range from -v ref / 2 to +v ref / 2. 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single- ended mode, input signal voltages are referred to gnd. in differential mode, the voltage dif- ference between two channels is measured. (tables 3 and 4.) selects clock and power-down modes. pd1 pd0 mode 00 full power-down (i dd = 2?, internal reference) 01 fast power-down (i dd = 30?, internal reference) 10 internal clock mode 11 external clock mode these three bits select which of the eight channels is used for the conversion (tables 3 and 4). the first logic 1 bit after cs goes low defines the beginning of the control byte. uni/ bip 3 sgl/ dif 2 pd1 pd0 1 0 (lsb) sel2 sel1 sel0 6 5 4 start 7 (msb) description name bit
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ______________________________________________________________________________________ 13 figure 6. 24-bit external clock mode conversion timing (microwire and spi compatible) simple software interface make sure the cpu? serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 100khz to 2mhz. 1) set up the control byte for external clock mode and call it tb1. tb1? format should be: 1xxxxx11 binary, where the xs denote the particular channel and conversion mode selected. 2) use a general-purpose i/o line on the cpu to pull cs on the max1202/max1203 low. 3) transmit tb1 and simultaneously receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb3. 6) pull cs on the max1202/max1203 high. figure 6 shows the timing for this sequence. bytes rb2 and rb3 contain the result of the conversion padded with one leading zero and three trailing zeros. the total conver- sion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. to avoid excessive t/h droop, make sure that the total conversion time does not exceed 120?. digital output in unipolar-input mode, the output is straight binary (figure 15); for bipolar inputs, the output is two?- complement (figure 16). data is clocked out at sclk? falling edge in msb-first format. the digital output logic level is adjusted with the vl pin. this allows dout and sstrb to interface with 3v logic without the risk of overdrive. the max1202/max1203? digital inputs are designed to be compatible with 5v cmos logic as well as 3v logic. internal and external clock modes the max1202/max1203 can use either an external ser- ial clock or the internal clock to perform the successive- approximation conversion. in both clock modes, the external clock shifts data in and out of the max1202/ max1203. the t/h acquires the input signal as the last three bits of the control byte are clocked into din. bits pd1 and pd0 of the control byte program the clock mode. figures 7?0 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, but it also drives the a/d conversion steps. sstrb pulses high for one clock period after the last bit of the control byte. successive-approximation bit decisions are made and appear at dout on each of the next 12 sclk falling edges (figure 6). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic low. figure 8 shows sstrb timing in external clock mode. sstrb sclk din dout 14 8 12 16 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb 1.5? (sclk = 2mhz) idle filled with zeros idle conversion t acq adc state cs rb1 rb2 rb3 acquisition
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 14 ______________________________________________________________________________________ figure 8. external clock mode sstrb detailed timing t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb figure 7. detailed serial-interface timing cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh the conversion must complete in some minimum time or droop on the sample-and-hold capacitors might degrade conversion results. use internal clock mode if the clock period exceeds 10? or if serial-clock interruptions could cause the conversion interval to exceed 120?. internal clock in internal clock mode, the max1202/max1203 generate their own conversion clock. this frees the ? from run- ning the sar conversion clock, and allows the con- version results to be read back at the processor? convenience, at any clock rate from zero to 2mhz. sstrb goes low at the start of the conversion, then goes high when the conversion is complete. sstrb is low for a maximum of 10?, during which time sclk should remain low for best noise performance. an internal regis- ter stores data while the conversion is in progress. sclk clocks the data out at this register at any time after the conversion is complete. after sstrb goes high, the next falling clock edge produces the msb of the conversion at dout, followed by the remaining bits in msb-first for- mat (figure 9). cs does not need to be held low once a
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ______________________________________________________________________________________ 15 figure 9. internal clock mode timing sstrb cs sclk din dout 14 8 12 18 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b11 msb b10 b9 b2 b1 b0 lsb acquisition 1.5? (sclk = 2mhz) idle filled with zeros idle conversion 10? max adc state 2 3 5 6 7 9 10 11 19 21 22 23 t conv figure 10. internal clock mode sstrb detailed timing pd0 clock in t sstrb t csh t conv t sck sstrb sclk t css note: keep sclk low during conversion for best noise performance. cs conversion is started. pulling cs high prevents data from being clocked into the max1202/max1203 and three- states dout, but it does not adversely affect an internal clock mode conversion already in progress. when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. figure 10 shows sstrb timing in internal clock mode. data can be shifted in and out of the max1202/max1203 at clock rates up to 2.0mhz, if t acq is kept above 1.5?. data framing cs ? falling edge does not start a conversion on the max1202/max1203. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conversion starts on sclk? falling edge after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as one of the following: the first high bit clocked into din with cs low any- time the converter is idle (e.g., after v dd is applied). or the first high bit clocked into din after bit 5 (b5) of a conversion in progress appears at dout. if a falling edge on cs forces a start bit before b5 becomes available, the current conversion is termi- nated and a new one started. thus, the fastest the max1202/max1203 can run is 15 clocks/conversion.
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 16 ______________________________________________________________________________________ figure 11a shows the serial-interface timing necessary to perform a conversion every 15 sclk cycles in exter- nal clock mode. if cs is low and sclk is continuous, guarantee a start bit by first clocking in 16 zeros. most microcontrollers (?s) require that data transfers occur in multiples of eight clock cycles; 16 clocks per conversion is typically the fastest that a ? can drive the max1202/max1203. figure 11b shows the serial-interface timing necessary to perform a conver- sion every 16 sclk cycles in external clock mode. __________ applications information power-on reset when power is first applied and if shdn is not pulled low, internal power-on reset circuitry activates the max1202/max1203 in internal clock mode, ready to convert with sstrb = high. after the power supplies are stabilized, the internal reset time is 100?. no con- versions should be performed during this phase. sstrb is high on power-up, and if cs is low, the first logical 1 on din is interpreted as a start bit. until a con- version takes place, dout shifts out zeros. reference-buffer compensation in addition to its shutdown function, shdn also selects internal or external compensation. the compensation affects both power-up time and maximum conversion speed. compensated or not, the minimum clock rate is 100khz due to droop on the sample-and-hold. float shdn to select external compensation. the typical operating circuit uses a 4.7? capacitor at ref. a value of 4.7? or greater ensures stability and allows converter operation at the 2mhz full clock speed. external compensation increases power-up time (see the section choosing power-down mode, and table 5). internal compensation requires no external capacitor at ref, and is selected by pulling shdn high. internal compensation allows for the shortest power-up times, but the external clock must be limited to 400khz during the conversion. power-down choosing power-down mode you can save power by placing the converter in a low- current shutdown state between conversions. select full power-down or fast power-down mode via bits 1 and 0 of the din control byte with shdn high or floating (tables 2 and 6). pull shdn low at any time to shut down the converter completely. shdn overrides bits 1 and 0 of the control byte. full power-down mode turns off all chip functions that draw quiescent current, reducing i dd and i ss typically to 2?. for the max1202, fast power-down mode turns off all circuitry except the bandgap reference. with fast power-down mode, the supply current is 30?. power-up time can be shortened to 5s in internal compensation mode. since the max1203 does not have an internal reference, power-up times coming out of full or fast power-down are identical. i dd shutdown current can increase if any digital input (din, sclk, cs ) is held high in either power-down mode. the actual shutdown current depends on the state of the digital inputs, the voltage applied to the digi- tal inputs (v ih ), the supply voltage (v dd ), and the operat- ing temperature. figure 12c shows the maximum i dd increase for each digital input held high in power-down mode for different operating conditions. this current is cumulative, so if all three digital inputs are held high, the additional shutdown current is three times the value shown in figure 12c. in both software power-down modes, the serial interface remains operational, but the adc does not convert. table 5 shows how the choice of reference-buffer com- pensation and power-down mode affects both power-up delay and maximum sample rate. in external compensa- tion mode, power-up time is 20ms with a 4.7? compen- sation capacitor (200ms with a 33? capacitor) when the capacitor is initially fully discharged. from fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2lsb while shut down. in power-down, the capacitor has to supply the current into the reference (typically 1.5?) and the transient currents at power-up. figures 12a and 12b show the various power-down sequences in both external and internal clock modes. software power-down software power-down is activated using bits pd1 and pd0 of the control byte. as shown in table 6, pd1 and pd0 also specify the clock mode. when software power-down is asserted, the adc continues to operate in the last specified clock mode until the conversion is complete. the adc then powers down into a low quies- cent-current state. in internal clock mode, the interface remains active and conversion results can be clocked out even though the max1202/max1203 have already entered software power-down. the first logical 1 on din is interpreted as a start bit and powers up the max1202/max1203. following the start bit, the control byte also determines clock and power-down modes. for example, if the din word con- tains pd1 = 1, the chip remains powered up. if pd1 = 0, power-down resumes after one conversion.
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ______________________________________________________________________________________ 17 figure 11a. external clock mode, 15 clocks/conversion timing figure 11b. external clock mode, 16 clocks/conversion timing hardware power-down the shdn pin places the converter into full power-down mode. unlike the software power-down modes, conver- sion is not completed; it stops coinciden tally with shdn being brought low. there is no power-up delay if an external reference, which is not shut down, is used. shdn also selects internal or external reference com- pensation (table 7). power-down sequencing the max1202/max1203? automatic power-down modes can save considerable power when operating at less than maximum sample rates. the following sec- tions discuss the various power-down sequences. lowest power at up to 500 conversions per channel per second figure 14a depicts max1202 power consumption for one or eight channel conversions using full power-down mode and internal reference compensation. a 0.01? bypass capacitor at refadj forms an rc filter with the internal 20k reference resistor, with a 0.2ms time con- stant. to achieve full 12-bit accuracy, 10 time constants (or 2ms in this example) are required for the reference buffer to settle. when exiting fullpd, waiting this 2ms in fastpd mode (instead of just exiting fullpd mode and returning to normal operating mode) reduces power con- sumption by a factor of 10 or more (figure 13). lowest power at higher throughputs figure 14b shows power consumption with external- reference compensation in fast power-down, with one and eight channels converted. the external 4.7? com- pensation requires a 50? wait after power-up. this cir- cuit combines fast multichannel conversion with the lowest power consumption possible. full power-down mode can increase power savings in applications where the max1202/max1203 are inactive for long periods of time, but where intermittent bursts of high-speed conver- sion are required. sclk din dout cs s control byte 0 control byte 1 s conversion result 0 conversion result 1 sstrb control byte 2 s 1 8181 b4 b5 b6 b7 b8 b9 b10 b11 b3 b2 b1 b0 b4 b5 b6 b7 b8 b9 b10 b11 b3 b2 b1 b0 cs sclk din dout s control byte 0 control byte 1 s conversion result 0 conversion result 1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b5 b6 b7 b8 b9 b10 b11 b1 b0
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 18 ______________________________________________________________________________________ table 6. software shutdown and clock mode table 5. typical power-up delay times table 7. hard-wired shutdown and compensation mode figure 12a. timing diagram for power-down modes, external clock powered up full power- down powered up powered up data valid (12 data bits) data valid (12 data bits) data invalid external external internal sx xxxx 11 s 01 xx x x x xx xxx s11 fast power-down mode dout din clock mode shdn sets external clock mode sets external clock mode sets fast power-down mode 133 2 full disabled 133 2 fast disabled 133 26 26 maximum sampling rate (ksps) see figure 14c 300 5 power-up delay (?) fast/full full fast power-down mode 4.7 ref capacitor (?) external enabled reference buffer internal enabled internal enabled reference-buffer compensation mode n/a full power-down gnd s s h h d d n n state external compensation enabled floating internal compensation enabled v dd reference-buffer compensation device mode external clock mode 1 1 internal clock mode 0 1 pd1 fast power-down mode 1 0 full power-down mode 0 0 device mode pd0
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ______________________________________________________________________________________ 19 external and internal references the max1202 can be used with an internal or external reference, whereas an external reference is required for the max1203. an external reference can be connected directly at the ref terminal, or at the refadj pin. an internal buffer is designed to provide 4.096v at ref for both the max1202 and the max1203. the max1202? internally trimmed 2.44v reference is buffered with a gain of 1.68. the max1203? refadj pin is buffered with a gain of 1.64, to scale an external 2.5v reference at refadj to 4.096v at ref. max1202 internal reference the max1202? full-scale range using the internal reference is 4.096v with unipolar inputs and ?.048v with bipolar inputs. the internal reference voltage is adjustable to ?.5% with the circuit of figure 17. figure 12b. timing diagram for power-down modes, internal clock figure 12c. additional i dd shutdown supply current vs. v ih for each digital input at a logic 1 figure 13. max1202 fullpd/fastpd power-up sequence full power-down powered up powered up data valid data valid internal clock mode sx xxxx 10 s 00 xx x x x s mode dout din clock mode sets internal clock mode sets full power-down conversion conversion sstrb 100 din refadj ref 2.5v 0v 4v 0v 101 1 1 1100 101 fullpd fastpd nopd fullpd fastpd 2ms wait complete conversion sequence t buffen ? 15? t = rc = 20k w x c refadj (zeros) ch1 ch7 (zeros) 0 -60 10 5 temperature (?) supply current per input ( m a) 100 25 20 15 -20 60 140 40 35 30 20 (v dd - v ih ) = 1.95v (v dd - v ih ) = 2.55v (v dd - v ih ) = 2.25v
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 20 ______________________________________________________________________________________ figure 14a. max1202 supply current vs. sample rate/second, fullpd, 400khz clock figure 14b. max1202/max1203 supply current vs. sample rate/second, fastpd, 2mhz clock external reference with both the max1202 and max1203, an external refer- ence can be placed at either the input (refadj) or the output (ref) of the internal reference-buffer amplifier. the refadj input impedance is typically 20k for the max1202, and higher than 100k for the max1203, where the internal reference is omitted. at ref, the dc input resistance is a minimum of 12k . during conversion, an external reference at ref must deliver up to 350? dc load current and have an output impedance of 10 or less. if the reference has higher output impedance or is noisy, bypass it close to the ref pin with a 4.7? capacitor. using the buffered refadj input makes buffering of the external reference unnecessary. when connecting an external reference directly at ref, disable the internal buffer by tying refadj to v dd . in power-down, the input bias current to refadj can be as much as 25? with refadj tied to v dd (max1202 only). pull refadj to gnd to minimize the input bias current in power-down. transfer function and gain adjust figure 15 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 16 shows the bipolar i/o transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary with 1lsb = 1.00mv (4.096v/4096) for unipo- lar operation, and 1lsb = 1.00mv [(4.096v/2 - -4.096v/ 2)/4096] for bipolar operation. figure 17 shows how to adjust the adc gain in applica- tions that use the internal reference. the circuit provides ?.5% (?5lsbs) of gain adjustment range. layout, grounding, and bypassing for best performance, use printed circuit boards. wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 18 shows the recommended system ground connections. establish a single-point analog ground 1000 1 0 100 300 500 full power-down 10 100 max186-14a conversions per channel per second 200 400 2ms fastpd wait 400khz external clock internal compensation 50 150 250 350 450 8 channels 1 channel average supply current (?) 10,000 10 0 max1202/max1203 fast power-down 100 1000 conversions per channel per second 2k 8 channels 1 channel 4k 6k 8k 10k 12k 14k 16k 18k 2mhz external clock external compensation 50? wait average supply current (?) 3.0 2.5 2.0 1.5 1.0 0.5 0 0.0001 0.001 0.01 0.1 1 10 time in shutdown (sec) power-up delay (ms) figure 14c. typical power-up delay vs. time in shutdown
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ______________________________________________________________________________________ 21 figure 16. bipolar transfer function, ?.096v/2 = full scale figure 15. unipolar transfer function, 4.096v = full scale (?tar?ground point) at gnd. connect all other analog grounds to this ground. no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low impedance and as short as pos- sible for noise-free operation. high-frequency noise in the power supplies can affect the adc? high-speed comparator. bypass these sup- plies to the single-point analog ground with 0.1? and 4.7? bypass capacitors close to the max1202/max1203. minimize capacitor lead lengths for best supply-noise rejection. if the +5v power supply is very noisy, a 10 resistor can be connected as a lowpass filter, as shown in figure 18. output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2lsb +4.096v + 4.096v 4096 fs = 1lsb = input voltage (lsbs) 011 . . . 111 output code 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0v input voltage (lsbs) +fs - 1lsb fs = +2.048v 1lsb = +4.096v 4096 +5v 510k 100k 24k 0.01? 12 refadj max1202 figure 17. max1202 reference-adjust circuit
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface 22 ______________________________________________________________________________________ tms320cl3x to max1202/ max1203 interface figure 19 shows an application circuit to interface the max1202/max1203 to the tms320 in external clock mode. figure 20 shows the timing diagram for this interface circuit. use the following steps to initiate a conversion in the max1202/max1203 and to read the results: 1) the tms320 should be configured with clkx (trans- mit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. the tms320? clkx and clkr are tied together with the max1202 /max1203s sclk input. 2) the max1202/max1203? cs is driven low by the tms320? xf_ i/o port to enable data to be clocked into the max1202/max1203? din. 3) write an 8-bit word (1xxxxx11) to the max1202/ max1203 to initiate a conversion and place the device into external clock mode. refer to table 2 to select the proper xxxxx bit values for your specific application. 4) the max1202/max1203? sstrb output is moni- tored via the tms320? fsr input. a falling edge on the sstrb output indicates that the conversion is in progress and data is ready to be received from the max1202/max1203. 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits repre- sent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) pull cs high to disable the max1202/max1203 until the next conversion is initiated. figure 19. max1202/max1203-to-tms320 serial interface +5v -5v +3v gnd supplies dgnd +3v vl v ss gnd v dd digital circuitry max1202 max1203 r* = 10 w *optional xf clkx clkr dx dr fsr cs sclk din dout sstrb tms320lc3x max1202 max1203 figure 18. power-supply grounding connection figure 20. tms320 serial-interface timing diagram cs sclk din sstrb dout start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 msb b10 b1 lsb high impedance high impedance
max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ______________________________________________________________________________________ 23 _ordering information (continued) v dd i/o sck (sk) mosi (so) miso (si) v ss shdn sstrb dout din sclk cs v ss vl gnd v dd refadj ch7 c3 0.1? c4 4.7? c5 0.1? ch0 +3v +5v c2 0.01? 0v to 4.096v analog inputs max1202 cpu c1 4.7? ref __________typical operating circuit ___________________chip information * dice are specified at t a = +25?, dc parameters only. ** contact factory for availability. transistor count: 2503 substrate connected to v ss part max1202aepp max1202bepp max1202aeap -40? to +85? -40? to +85? -40? to +85? temp. range pin-package 20 plastic dip 20 plastic dip 20 ssop max1202beap -40? to +85? 20 ssop max1202bmjp -55? to +125? 20 cerdip** inl (lsb) ?/2 ? ?/2 ? ? max1203 acpp max1203bcpp max1203acap 0? to +70? 0? to +70? 0? to +70? 20 plastic dip 20 plastic dip 20 ssop max1203bcap 0? to +70? 20 ssop max1203bc/d 0? to +70? dice* ?/2 ? ?/2 ? ? max1203aepp max1203bepp max1203aeap -40? to +85? -40? to +85? -40? to +85? 20 plastic dip 20 plastic dip 20 ssop max1203beap -40? to +85? 20 ssop max1203bmjp -55? to +125? 20 cerdip** ?/2 ? ?/2 ? ?
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. max1202/max1203 5v, 8-channel, serial, 12-bit adcs with 3v digital interface ________________________________________________________package information pdipn.eps ssop.eps

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